1. Field of the Invention
The present invention relates to a semiconductor device using a plurality of high-potential-side reference voltages.
2. Description of the Related Art
A reduction in power consumption is required for an LSI (Large Scale Integration) mounted on electronic equipment. In particular, the reduction in power consumption is strongly required for LSIs mounted on battery-driven mobile devices for the purpose of securing the extended battery life. As one of methods for reducing the power consumed by the LSIs, a plurality of power supply voltages are used and a lower one of the plurality of supply voltages is used when parts, in the LSI where not so much precision is required, is to be controlled.
For example, a method has been proposed where a lower power supply voltage in the plurality of power supply voltages is used and thereby the amplitude of a clock signal is made small. A large portion of electric power consumed within the LSI is consumed as power for the charging and discharging of gate capacitances used for turning on and off gates of transistors by clock signals. The power consumed by the charging and discharging by the clock signals is proportional to the square of power supply voltage. Thus, the reduction in the amplitude of clock signal will be effective in the reduction of power consumed by the charging and discharging.
As described above, when circuitry having a plurality of power supply voltages mixed therein is to be designed, the layout of power supply lines is complex as compared with a case where a single type of power supply voltage is used. Depending on the wiring position, the degree of freedom in component arrangement may be deteriorated or increased area of circuitry may result.
As the power line is located farther away from the power supply, the power supply voltage level thereof deteriorates as compared with the original level. To reduce this adverse effect, there is a method where, for a circuit having the multiplicity of elements arranged therein, the power lines are arranged in a mesh topology.